LDMOS transistors (lateral double-diffused MOS transistors) have a high switching speed. Furthermore, the LDMOS transistors are easy to use because they are voltage-driven. Because of such features, LDMOS transistors have been used in such devices as switching regulators, various drivers, and DC-DC converters. LDMOS transistors are widely used as a key device in fields of power devices and high-breakdown-voltage devices.
In general, performance of an LDMOS transistor is expressed in terms of (i) its withstanding voltage (breakdown voltage) observed in the off-state and (ii) its on-resistance. However, since there is normally a trade-off between them, it is difficult to achieve a high withstanding voltage and a low on-resistance at the same time. In view of this, research has been conducted for many years on how to achieve them at the same time.
FIGS. 15, 16 (a), 16 (b) and 17 illustrate a conventional LDMOS transistor (see, for example, Patent Literature 1). FIG. 15 is a schematic plan view of the n-channel LDMOS transistor formed on a p-type semiconductor substrate. FIGS. 16 (a) and 16 (b) are each a schematic cross-sectional view taken along line L1-L2 of FIG. 15 (a length direction of the channel of the LDMOS transistor, i.e., a source-drain direction; hereinafter referred to also as an L direction). FIG. 17 is a schematic cross-sectional view taken along line W1-W2 of FIG. 15 (a width direction of the channel of the LDMOS transistor, i.e., a direction perpendicular to the source-drain direction; hereinafter referred to also as a W direction).
As illustrated in FIG. 16 (a), the n-channel LDMOS transistor includes: a p-type semiconductor substrate 1; a p-type epitaxial layer 2 disposed on the p-type semiconductor substrate 1; and a p-type buried diffusion region 4 disposed along the interface between the p-type semiconductor substrate 1 and the p-type epitaxial layer 2.
The n-channel LDMOS transistor further includes within the p-type epitaxial layer 2: a p-type body region 6; a p-type diffusion region 4a formed so as to electrically connect the p-type body region 6 and the p-type buried diffusion region 4 to each other in a suitable manner; and an n-type drift region 7 formed separately from the p-type body region 6 along a planar direction.
The n-channel LDMOS transistor also includes an n-type source region 8 and a p-type body contact region 9 within the p-type body region 6, and further includes an n-type drain region 10 within the n-type drift region 7. The n-channel LDMOS transistor further includes a gate electrode 11 above the p-type body region 6 with a gate insulating film interposed between them.
The n-channel LDMOS transistor also includes a source contact 8b and a source electrode 8a formed on the n-type source region 8 and the p-type body contact region 9. The source electrode 8a electrically connects the n-type source region 8 and the p-type body region 6 with each other so that the n-type source region 8 and the p-type body region 6 have a same potential. The n-channel LDMOS transistor further includes a drain contact 10b and a drain electrode 10a formed on the n-type drain region 10 and also includes a gate plate 12 between the source electrode 8a and the drain electrode 10a. 
Generally, in measuring the withstanding voltage of the n-channel LDMOS transistor in an off-state, the source electrode 8a and the gate electrode 11 are set to a GND potential, while the drain electrode 10a is provided with a positive potential. In this state, application of a reverse bias between the drain and the source causes an electric field within a depletion layer to reach its critical electric field strength at a certain voltage. This causes an avalanche breakdown, which results in a large amount of current flowing between the drain and the source. The above certain voltage applied is referred to as a withstanding voltage of the transistor.
Application of a reverse bias between the drain and the source along the L direction of the LDMOS transistor generally causes concentration of an electric field at a gate edge on a drain side (indicated as A in FIG. 16 (a)). This lowers the withstanding voltage.
Therefore, relaxing the electric field at the gate edge is an important factor to have a higher withstanding voltage. In addition, such concentration of an electric field near the gate edge may cause some electric charge to be left in the gate insulating film. This gives rise to a reliability problem. Thus, relaxing the electric field at the gate edge is important also for improvement of reliability of the transistor.
FIG. 16 (b) partially illustrates equipotential lines (indicated by dashed lines) of a potential along the L direction, which equipotential lines are obtained when the source electrode 8a and the gate electrode 11 of the LDMOS transistor are set to the GND potential and a positive potential is applied on the drain electrode 10a. 
Application of a reverse bias between the drain and the source causes a depletion layer to extend from the p-type body region 6. As illustrated in FIG. 16 (b), the presence of the p-type buried diffusion region 4 and the gate plate 12 facilitates shifting the depletion layer toward the drain electrode 10a for relaxation of the surface electric field. As a result, the electric field at the gate edge on the drain side (indicated as A in FIG. 16 (b)) is relaxed. This attains a withstanding voltage, and also attains a better trade-off between the withstanding voltage and the on-resistance. In these respects, this technique is effective.
FIGS. 18, 19 (a), 19 (b), 20 (a), and 20 (b) illustrate another conventional LDMOS transistor (see, for example, Patent Literature 2). FIG. 18 is a schematic plan view of the n-channel LDMOS transistor formed on a p-type semiconductor substrate. FIGS. 19 (a) and 19 (b) are each a schematic cross-sectional view taken along line L1-L2 of FIG. 18. FIGS. 20 (a) and 20 (b) are each a schematic cross-sectional view taken along line W1-W2 of FIG. 18.
As illustrated in FIG. 19 (a), the LDMOS transistor includes: a p-type semiconductor substrate 101; an n-type epitaxial layer 102 disposed above the p-type semiconductor substrate 101; and an n-type high-density buried diffusion layer 103 disposed along an interface between the p-type semiconductor substrate 101 and the n-type epitaxial layer 102.
The n-type epitaxial layer 102 includes: a p-type buried diffusion region 104; an n-type diffusion region 105 formed adjacently to the p-type buried diffusion region 104; a p-type body region 106 formed in contact with the p-type buried diffusion region 104; and an n-type drift region 107 formed adjacently to the p-type body region 106.
The n-channel LDMOS transistor also includes an n-type source region 108 and a p-type body contact region 109 within the p-type body region 106, and further includes an n-type drain region 110 within the n-type drift region 107.
The n-channel LDMOS transistor further includes a gate electrode 111 above the p-type body region 106 with a gate insulating film interposed between them. The n-channel LDMOS transistor also includes a drain contact 110a and a drain electrode 110b above the n-type drain region 110, and further includes a source contact 108a and a source electrode 108b above the n-type source region 108 and the p-type body contact region 109. The source electrode 108b electrically connects the n-type source region 108 and the p-type body region 106 to each other at a same potential.
The LDMOS transistor is largely different from the above-described conventional LDMOS transistor (see, for example, Patent Literature 1) in that the p-type body region 106 formed within the n-type epitaxial layer 102 is electrically isolated from the p-type semiconductor substrate 101 in a suitable manner. According to the conventional LDMOS transistor disclosed in Patent Literature 1 (see FIGS. 15, 16 (a), 16 (b) and 17), the p-type body region 6 is electrically connected to the p-type semiconductor substrate 1 via the p-type diffusion region 4a and the p-type buried diffusion region 4 in a suitable manner. Since the p-type semiconductor substrate 1 is normally fixedly set to the GND potential, the p-type body region 6 and the n-type source region 8 are also fixedly set to the GND potential.
When multiple n-channel transistors are arranged in series between, for example, a power supply and GND in a circuit configuration, an n-channel transistor that is the first one from the power supply has a potential in the source region in an on-state, which potential is substantially fixed to the power supply voltage. Thus, the source region is required to have a withstanding voltage, which is voltage difference between the source region and the p-type semiconductor substrate (which is normally set to the GND potential), high enough for withstanding the power supply voltage.
When, as mentioned above, the source region is required to have a withstanding voltage high enough for withstanding the power supply voltage unlike the p-type semiconductor substrate (which is normally set to the GND potential), the conventional LDMOS transistor disclosed in Patent Literature 1 cannot be used since the source region is electrically connected to the p-type semiconductor substrate (which is normally set to the GND potential) and therefore fixedly set to the GND potential.
In contrast, according to the conventional LDMOS transistor disclosed in Patent Literature 2, the source region is electrically isolated from the p-type semiconductor substrate (which is set to the GND potential). This allows the LDMOS transistor to be used even when the source region is required to have a withstanding voltage high enough for withstanding the power supply voltage. Thus, the conventional LDMOS transistor disclosed in Patent Literature 2 has an advantage over the conventional LDMOS transistor disclosed in Patent Literature 1 in that the former has a wider application in circuit.
FIG. 19 (b) partially illustrates equipotential lines (indicated by dashed lines) of a potential along the L direction (direction L1-L2 of FIG. 18), which equipotential lines are obtained when a reverse bias is applied between the drain and the source of the conventional LDMOS transistor disclosed in Patent Literature 2. The p-type buried diffusion region 104 facilitates shifting a depletion layer toward a drain side. This sufficiently relaxes an electric field at a gate edge (indicated as A in FIG. 19 (b)) and thereby likely improves the withstanding voltage.
Citation List
Patent Literature 1
Japanese Patent Application Publication, Tokukaihei, No. 7-50413 A (Publication Date: Feb. 21, 1995)
Patent Literature 2
Patent No. U.S. Pat. No. 6,979,875B2 (Issuance Date: Dec. 27, 2005)